A number of devices, for instance mobile applications such as portable devices, require the use of a frequency synthesizer for operation. One such frequency synthesizer includes a digital-to-phase converter (DPC). FIG. 1 illustrates a block diagram of a prior art DPC 100 configuration for generating an output signal 42 at a desired frequency Fout. DPC 100 comprises a fixed frequency source 10 for generating a clock signal 12 having a frequency of Fref. Clock signal 12, thus, comprises a plurality of successive clock pulses having a rising edge and a falling edge and occurring at a frequency Fref. Clock signal 12 is further characterized by a plurality of corresponding successive clock cycles that each begins with a rising edge of one of the clock pulses and ends with the rising edge of the next clock pulse.
DPC 100 further comprises: a tapped delay line 20 having M number of adjustable delay elements (not shown); a multiplexer 40 (also referred to herein as a “MUX”); and a digital control device or digital block 30 such as, for instance, an accumulator-based processor. It should be understood by those of ordinary skill in the art that DPC 100 typically includes additional conventional elements that are not shown for the sake of brevity. For instance, delay line 20 is typically a part of a delay-locked loop (DLL) that also typically includes a phase detector, a charge pump and a low pass filter, which make up a stabilization circuit for the DLL.
In operation, delay line 20 receives the clock signal 12 into an input and then generates a set of time delayed (or phase-shifted) clock signals at a plurality of output taps illustrated as Taps[0:M−1]. The time delays are generated by the delay elements in delay line 20, which are connected in cascade and which may be, for instance, inverter gates, transmission line structures, and the like, depending upon a desired DPC implementation. Moreover, an overall time delay between a signal at a first point on the delay line, which is typically an input of a first delay element, e.g., D1, and a signal at a second point on the delay line, which is typically the output of the Mth delay element, e.g., DM, is controlled by a control signal, e.g., a bias voltage, input into delay line 20. This overall delay may be, for instance, a wavelength (i.e., 360 degrees) which is one period of clock signal 12, a half wavelength (i.e., 180 degrees) which is one half period of clock signal 12, or whatever delay is required for a particular application. Ideally, each delay element will replicate the input waveform with a time delay at the delay element output that is equal to the total delay from the input of the first delay element through the output of the last delay element divided by the total number of delay elements (i.e., M).
Typically, delay elements D1-D(M−1) each have a corresponding output tap T[1]-T[M−1], respectively, which is connected to an input of MUX 40. In addition, a tap T[0] is typically connected between the input of the delay element D1 and an input of MUX 40. Each delay element D1-D(M−1) delays the propagation of the clock signal 12 and outputs on its corresponding output tap T[1]-T[M−1], respectively, a corresponding phase-shifted clock signal. Accordingly, the number M−1 of phase-shifted clock signals output by delay elements D1-D(M−1) are supplied via output taps T[1]-T[M−1] to the inputs of MUX 40 along with the clock signal 12 output (i.e., having a zero time delay) on tap T[0].
MUX 40 operates in a conventional way under the control of digital block 30 using a digital control signal 32 to connect, one at a time, a sequence of phase-shifted clock signals to an output of MUX 40 to provide an output signal 42 at the desired output frequency Fout. Digital block 30 is typically a tap selection controller that comprises digital processing to determine a tap to connect to an output of MUX 40. Digital block 30 then generates and provides to MUX 40 a digital control signal 32 (also referred to herein by the notation dig_ctl[0:M−1]) on one or more digital control lines, which identifies which tap to select (e.g., Taps[0:M−1]). The end result of this implementation is the generation of a multiplicity of clock edges (or pulses) that are delayed in time generally over one period of the input reference clock.
When generating the output signal 42, there is a phase/timing relationship that must be maintained between the clock signal 12 that drives the digital block 30 and the phase-shifted clock signal that propagates down the delay line 20 to an output of MUX 40. This phase/timing relationship is maintained by a proper windowing technique. Windowing is defined herein as opening a path to an output of MUX 40 early enough and closing that path late enough so that all of a desired phase-shifted clock pulse and none of a proceeding or later pulse is seen at the output of the MUX.
Referring again to DPC 100 illustrated in FIG. 1, under certain circumstances a windowing error may occur when MUX 40 uses control signal 32 to open a window of time within which a phase-shifted clock signal pulse is to be sent to an output of MUX 40. For example, let's assume that the delay line 20 is locked to one wavelength of clock signal 12 and that there are 32 output taps. In this embodiment, control signal 32 is synchronized with the leading edge of clock signal 12, and no more than one output pulse 42 is generated for every cycle of clock signal 12. A windowing error will generally not occur when MUX 40 selects output taps from the first half (i.e., taps T[0] through T[15]) of the delay line 20, where the rising and falling edges of the phase-shifted clock signals from taps T[0] through T[15] occur within a single cycle duration of control signal 32. However, a windowing error may occur when MUX 40 selects an output tap from the second half (i.e., taps T[16] through T[31]) of the delay line 20, where the falling edge of the phase-shifted clock signals from taps T[16] through T[31] occur after the falling edge of the control signal 32. Waveforms 200-250 in FIG. 2 illustrate such a windowing error.
Waveform 200 represents clock signal 12. Waveform 240 represents the desired output signal 42, and waveform 250 represents the actual output signal 42. Accordingly, in an attempt to generate the first pulse of the desired output signal 42, the digital block 30 of DPC 100 generates a digital control signal 32 represented by waveform 210 and labeled dig_ctl[0] for use by MUX 40 to generate that first pulse. Under the control of dig_ctl[0], MUX 40 will be directed to select output Tap[0], which in this instance is the output tap corresponding to clock signal 12 (i.e., waveform 200). Moreover, in this embodiment, the width of the pulse and location of the pulse in time determines the time during which the signal from Tap[0] will be sent to an output of MUX 40. As can be seen by waveform 250, under the control of the first control signal 32 (i.e., dig_ctl[0]), MUX 40 captures the desired pulse from Tap[0] (that is circled in waveform 200 with an arrow drawn to the corresponding pulse in waveform 240) thereby causing the actual output pulse to be the desired output pulse.
This is not the case when generating the second pulse of output signal 42. In an attempt to generate the second pulse of the desired output signal 42, the digital block 30 of DPC 100 generates a digital control signal 32 represented by waveform 230 and labeled dig_ctl[24] for use by MUX 40 to generate that second pulse. Under the control of dig_ctl[24], MUX 40 will be directed to select output Tap[24]. However as can be seen from waveform 250, the width and the location in time of the dig_ctl[24] pulse causes MUX 40 to capture only a portion of the desired pulse from Tap[24] (that is circled in waveform 220 with an arrow drawn to the corresponding pulse in waveform 240) and to also capture a portion of the preceding pulse. Thus, the windowing error resulting from the timing of dig_ctl[24] causes a corresponding error in the actual output signal 42 as illustrated in waveform 250.
Known windowing apparatus (not shown) used with DPC 100 comprises a replica of the primary delay line 20 on each digital control line from digital block 30. Accordingly, to perform windowing the control signal for output Tap[1] is delayed using one delay element from its corresponding delay line. The control signal for output Tap[2] is delayed using two delay elements from its corresponding delay line, and likewise for the remaining output taps in the delay line. Thus, the DPC uses output taps from these secondary delay lines to open and close a window of time for the phase-shifted clock signal from each tap selection from the primary delay line 20 to be passed to the MUX output. Where there are M control lines for M output taps, a minimum of M/2 additional delay lines are needed in the DPC causing an M/2 increase in area and power dissipation of the DPC. For multiple independent output terminals of MUX 40 sharing a common tapped delay line requiring separate tap selection networks, such a windowing scheme is completely impractical.
Thus, there exists a need for a method and apparatus for use in a DPC that addresses the above-identified windowing errors and corresponding error in output signals generated by frequency synthesizers known in the art and that does not require the use of secondary delay lines that increase the size of the DPC and its power dissipation.